1. Field of the Invention
The present invention relates to a method for producing small memory arrays embedded on masterslices.
2. Description of the Prior Art
Digital integrated circuits are becoming increasingly dense as a consequence of continuing miniaturization of integrated components and integrated line widths. As a result, these circuits are becoming increasingly sophisticated. Such circuits are typically fabricated using one of two techniques: use of a fully customized chip or use of a masterslice. The custom chip technique requires that the chip be completely designed for the particular circuit, i.e. the integrated circuit elements themselves (e.g. the transistors and resistors , their layout and their interconnect lines are dictated solely by the particular circuit being implemented. This technique produces chips having a higher density than those produced using the masterslice technique. However, this custom chip technique, particularly for large and dense integrated circuits, necessitates expensive and time consuming engineering and manufacturing efforts.
In contrast, the masterslices techique involves fabricating a number of closely spaced identical cells in an array configuration over a relatively large section of the available area on each chip. Each cell contains an identical arrangement of various integrated elements, such as transistors, diodes and/or resistors. Through a particular metallization layer applied over the surface of each cell, the components situated therein can be interconnected to form a specific logic circuit, e.g. a single bit register, a gate, a single bit memory cell and the like. Thereafter, another metallization layer is applied over the surface of the masterslice to interconnect the cells in a particular pre-defined pattern in order to implement one or more given functions, e.g. multi-bit registers, random access memories, and large shift registers. A portion of a masterslice can be allocated to any given function and, as such, several different circuits can exist on one masterslice. Consequently, masterslices can be used to implement a wide variety of different digital circuits. Because a masterslice contains a pre-defined regularly ordered arrangement of identical cells, with only the multi-layer metallization pattern being dictated by the application, masterslices can be easily and inexpensively designed using an automated design process. Although the masterslice technique produces somewhat lower density chips than does the custom chip technique, the masterslice technique offers substantial cost and time savings in the design of a dense chip over those associated with the custom chip technique. These savings quickly become substantial when a large number of different dense large scale integrated circuit (LSI) chips need to be designed and manufactured. As a result, sophisticated logic circuits can be manufactured using the masterslice technique at a fraction of the time and at a substantial cost saving over that required by the custom chip design technique. Hence, for those reasons, an increasing number of dense logic chips are being designed using the masterslice technique.
Oftentimes, an integrated circuit requires a small amount of memory to implement a specialized function, such as a stack or small cache memory. In the past, without masterslices, such memories were implemented using either special on-chip registers or latches, or through specialized off-chip circuitry. Unfortunately, on-chip registers consumed an inordinate amount of chip area and also increased the power consumed by the chip; while, alternatively, routing signals to off-chip circuitry decreased the speed at which the integrated circuit could operate.
Masterslices permit large and small memory arrays to be embedded on an integrated circuit chip. This eliminates the need to construct these memories from on-chip registers and thereby reduces any adverse affect of the memory on the amount of power consumed by the chip. Either one of two separate approaches, both well known in the art, is often used to implement such memories on a masterslice. Each approach possesses various drawbacks.
Specifically, the first approach relies on allocating a specific area on the masterslice only to memories. No other circuits could be implemented in this area. Hence, if memories smaller than this area are implemented, then any remaining area is simply not used. Consequently, chip area is wasted. Clearly, the amount of wasted area depends upon the size of the necessary memory; the smaller the memory, the more area that is wasted. Moreover, this approach only permits the memory to be located in a specific region on the masterslice. Consequently, this leads to a fairly rigid set of layout constraints. In addition, if a memory requires more area than that allocated on the chip, then off-chip memory is used which disadvantageously imparts a speed penalty to the entire memory.
The alternate approach for embedding memories in masterslices involves implementing the memory using pre-defined memory array macros (pre-defined multi-layer metallization patterns) that can be located anywhere on the masterslice. Each macro produces a small complete memory of a pre-determined size that can be interconnected to memory arrays produced by other memory array macros in order to form large memory arrays. Unfortunately, the smallest memory array macro that is often used (illustratively 16 by 9 bits) is frequently too large to implement some small (e.g. 16 by 6 bit) on-chip memories. The remedy for this is to design either an entirely customized memory array or a new smaller memory array macro, or simply utilize an existing memory array macro that has more locations than necessary. The first two remedies consume excessive engineering time and are therefore to be avoided; while the third remedy only wastes chip area and power. For that reason, the third remedy is frequently taken although it yields an inefficient chip layout.
Thus, a need exists in the art for a method for producing a small embedded memory which can be located anywhere on the masterslice and contains only the exact number of memory locations that are required.